In a typical microcontroller a reset scheme will be implemented whereby on receiving of a particular event the microcontroller will be reset. In more intelligent systems this scheme may be split into separate levels of reset, some of which may require that a portion of the chip still be functional during the reset.
The limitation is that this former type of reset may cause a voltage overshoot beyond the operational range of the chip due to the sudden drop in switching activity caused by clock frequency reduction (or stopping) and large portions of the logic being held in their reset state. The follow-on result is that a more severe level of reset may be triggered by this voltage overshoot, thus eliminating the advantages of having less severe levels of reset and making it difficult for software to determine the original cause of the reset.
The phenomenon described above has already been observed on 90 nm CMOS devices, and the trend towards smaller technologies and more cores on single chips is making the problem more acute. A solution that is currently used is a very cumbersome software sequence.